1. Field of the Invention
The present invention relates to a voltage comparator, and, more particularly, to a voltage comparator which operates at a high speed and is suitable for integration.
2. Description of the Related Art
A voltage comparator related with the present invention has been discussed in IEEE Journal of Solid State Circuits, Vol. SC-17, No. 6, Dec. 1982, pp. 1080-1087.
FIGS. 2A and 2B show a configuration and operating waveforms of a voltage comparator which was considered by the inventors.
The voltage comparator shown in FIG. 2A is constructed of a switch SW1 and a hold capacitor C1 for sampling and holding an input signal V1, switches SW2a and SW2b which provide input signals V1 and V2 to input terminals of a differential amplifier 1, while switching them to each other, a hold capacitor C2 which holds the input signals V1 and V2, differential amplifiers 1 and 2, A.C. coupling capacitors 3 and 4 which couple the differential amplifier 1 and the differential amplifier 2 with each other, switches SWA1 and SWA 2 which make a short-circuit between the input and the output of the differential amplifier 2, and a latch circuit 20 which fetches and defines the output result of the differential amplifier 2.
The voltage comparing operation of the voltage comparator shown in FIG. 2A will be described in detail hereafter with reference to an operating waveform diagram shown in FIG. 2B.
In the voltage comparator, the switches SW1, SW2a , SWA1 and SWA2 turn on, the switch SW2b turns off, the input signal V1 is applied to both input terminals of the differential amplifier 1, and almost equal output voltages are generated at both output terminals of the differential amplifier 1 in the initial period I. Since both the switches SWA1 and SWA2 are turned on, both input voltages of the differential amplifier 2 are set equal to each other at both output voltages, and both input-output voltages of the differential amplifier 2 are self-biased at an equal voltage.
In the next period II, the switches SW1 and SW2a turn off, and the input signal V1 is held equally by hold capacitors C1 and C2 at both input terminals of the differential amplifier 1. At this time, switching charge generated from the switches SW1 and SW2a can be absorbed by the capacitors 3 and 4.
In the next period III, the switches SWA1 and SWA2 turn off, to thereby eliminate short-circuiting between the input and the output of the differential amplifier. Further, the switch SW2b turns on, and an input signal V2 is initiated to be applied (sampled) to the hold capacitor C2 at the input terminal of the differential amplifier 1.
In the next period IV, the switch SW2b turns off, the value of the input signal V2 is suspended to be sampled to the hold capacitor C2 at the input terminal of the differential amplifier 1 and the input signal V2 immediately before the switch SW2b turns off is held by the hold capacitor C2 at the input terminal of the differential amplifier 1. As a result, the input differential voltage which is held by both input terminals of the differential amplifier 1 is amplified by means of the differential amplifier 1, and the magnitudes of the input signals V1 and V2 are judged through the differential amplifiers 1 and 2 and the latch circuit.